參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 27/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
27
Signal Name
Type
Description
GGNT#
GMDA
O
AGP
I/OD
CMOS
Grant
:
During SBA, PIPE# and FRAME# Operation: GGNT
#
along with the information on
the ST[2:0] signals (status bus) indicates how the AGP interface will be used next.
Refer to the AGP Interface Specificaiton revision 2.0 for further explanation of the
ST[2:0] values and their meanings.
GMBUS
: When configured by register GMBUS[2:0], GMDA becomes a bidirectional
I/O data signal between master GMCH2-M and slave VCH.
GAD [31:0]
I/O
AGP
Address/Data Bus
:
During PIPE# and FRAME# Operation: GAD[31:0] are used to transfer both
address and data information on the AGP inteface.
During SBA Operation: GAD[31:0] are used to transfer data on the AGP interface.
GCBE [3:0]#
I/O
AGP
Command/Byte Enable:
During FRAME# Operation:
During the address phase of a transaction, GCBE[3:0]#
define the bus command. During the data phase GCBE[3:0]# are used as byte
enables. The byte enables determine which byte lanes carry meaningful data. The
commands issued on the GCBE# signals during FRAME# based AGP are the same
GCBE# command described in the PCI 2.1 and 2.2 specifications.
During PIPE# Operation:
When an address is enqueued using PIPE#, the C/BE#
signals carry command information. Refer to the AGP 2.0 Interface Specification
Revision 2.0 for the definition of these commands. The command encoding used
during PIPE# based AGP is
DIFFERENT
than the command encoding used during
FRAME# based AGP cycles (or standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA operation.
GPAR
I/O
AGP
Parity
:
During FRAME# Operation:
GPAR is driven by the GMCH2-M when it acts as a
FRAME# based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. GPAR is driven by the GMCH2-M when
it acts as a FRAME# based AGP target during each data phase of a FRAME#
based AGP memory read cycle. Even parity is generated across GAD[31:0] and
GCBE[3:0]#.
During SBA and PIPE# Operation:
This signal is not used during SBA and PIPE#
operation.
NOTES:
1. LOCK#, SERR#, and PERR# signals are not supported on the AGP Interface (even for PCI operations).
2. PCI signals described in this table behave according to PCI 2.1 specifications when used to perform PCI
transactions on the AGP interface.
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