參數(shù)資料
型號(hào): 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù): 119/163頁(yè)
文件大?。?/td> 1049K
代理商: 82815EM
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Intel
82815EM GMCH
R
Datasheet
119
Optional larger write-back cacheable TSEG area of either 512 KB or 1MB in size above 1MB that
is reserved from the highest area in system DRAM memory. The above 1MB solutions require
changes to compatible SMRAM handlers code to properly execute above 1MB.
The hub interface and AGP masters are not allowed to access the SMM space. This must be insured even
for the GTLB translation.
4.4.1.
SMM Space Definition
SMM space has
addressed
SMM space and
DRAM
SMM space. The addressed SMM space is the
range of bus addresses used by the processor to access SMM space. DRAM SMM space is the range of
physical DRAM memory locations containing the SMM code.
SMM space can be accessed at one of three transaction address ranges: Compatible, HSEG and TSEG.
The Compatible and TSEG SMM space is not remapped. Therefore the addressed and DRAM SMM
space is the same address range. Since the HSEG SMM space is remapped, the addressed and DRAM
SMM space is a different address range. Note that the HSEG DRAM space is the same as the
Compatible Transaction Address space. Therefore the table below describes three unique address ranges:
Compatible Transaction Address (Adr C)
High Transaction Address (Adr H)
TSEG Transaction Address (Adr T)
These abbreviations are used later in the table describing SMM Space Transaction Handling.
Table 11. SMM Space Abbreviations
SMM Space Enabled
Transaction Address Space (Adr)
DRAM Space (DRAM)
Compatible (C)
A_0000h to B_FFFFh
A_0000h to B_FFFFh
High (H)
0FEE_A0000h to 0FEE_BFFFFh
A_0000h to B_FFFFh
TSEG (T)
(TOM-TSEG_SZ) to TOM
(TOM-TSEG_SZ) to TOM
If the GMCH2-M is operating in internal graphics mode, a 512Kb or 1Mb window can optionally be
used for the display frame buffer. This window is taken after the TSEG window.
4.4.2.
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and may
cause the system to hang:
The Compatible SMM space must not be set-up as cacheable.
HSEG or TSEG SMM transaction address space must not overlap address space assigned to system
DRAM, the AGP aperture range, or to any “PCI” devices (including the hub interface and AGP
devices). This is a BIOS responsibility.
When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available
DRAM. This is a BIOS responsibility.
Any address translated through the AGP Aperture GTLB must not target DRAM from 000A_0000h
to 000F_FFFFh.
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