參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 29/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
29
2.4.
Display Cache Interface Signals
Some of the Display Cache interface signals are multiplexed with AGP interface signals. Display Cache
interface signals only function as documented in this section when Intel
815EM chipset integrated
graphics is enabled (Intel
815EM chipset AGP interface disabled). Refer to Section 2.12 for
multiplexing map of AGP to Display Cache interface signals.
Signal Name
Type
Description
LCS#
O
CMOS
Chip Select:
For the memory row configured with SDRAM, this pin performs the
function of selecting the particular SDRAM components during the active state.
LDQM[3:0]
O
AGP
Input/Output Data Mask:
These pins control the memory array and act as
synchronized output enables during read cycles and as a byte enables during write
cycles.
LRAS#
O
CMOS
SDRAM Row Address Strobe:
The LRAS# signal is used to generate SDRAM
Command encoded on LRAS#/LCAS#/LWE# signals. When LRAS# is sampled
active at the rising edge of the SDRAM clock, the row address is latched into the
SDRAMs.
LCAS#
O
CMOS
SDRAM Column Address Strobe:
The LSCAS# signal is used to generate
SDRAM Command encoded on LSRAS#/LSCAS#/LWE# signals. When LSCAS# is
sampled active at the rising edge of the SDRAM clock, the column address is
latched into the SDRAMs.
LMA[11:0]
O
AGP
Memory Address:
LMA[11:0] is used to provide the multiplexed row and column
address to SDRAM.
LWE#
O
CMOS
Write Enable Signal:
LWE# is asserted during writes to SDRAM.
LMD[31:0]
I/O
AGP
Memory Data:
These signals are used to interface to the SDRAM data bus of
SDRAM array.
L_FSEL
I
CMOS
Display Cache Frequency Select:
This signal indicates whether the display cache
is to run at 100MHz or 133MHz. The value of this pin is sampled at de-assertion of
CPURST# to determine display cache frequency.
HIGH = 133MHz (Default)
LOW = 100MHz
Note: L_FSEL has a weak internal pull-up enabled during reset.
Note: 100MHz display cache is a non-validated feature and should be implemented
only if OEM performs validation specifically on this feature.
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