參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 128/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
128
Datasheet
4.9.
System Memory DRAM Interface
The GMCH2-M integrates a system DRAM controller that supports a 64-bit DRAM array. The DRAM
type supported is Synchronous (SDRAM). The GMCH2-M generates the SCSA#, SCSB#, SDQM,
SCAS#, SRAS#, SWE# and multiplexed addresses, SMA for the DRAM array. The GMCH2-M’s
DRAM interface operates at a clock frequency of 100MHz, dependent upon the system bus interface
clock frequency. The DRAM controller interface is fully configurable through a set of control registers.
Complete descriptions of these registers are given in the register description section of this document.
The GMCH2-M supports industry standard 64-bit wide SO-DIMM modules with SDRAM devices. The
2 bank select lines SBS[1:0], the 12 Address lines SMAA[11:0], and copies of 4 Address lines
SMAB[7:4]# and SMAC[7:4]# allow the GMCH2-M to support 64 bit wide SO-DIMMs using 16Mb,
64Mb, 128Mb or 256Mb technology SDRAMs. The GMCH2-M has a sufficient amount of SCS# lines
to enable the support of up to six 64-bit rows of DRAM. For write operations of less than a Qword in
size, the GMCH2-M will perform a byte-wise write. The GMCH2-M targets SDRAM with CL2 and CL3
and supports both single and double-sided SO-DIMMs. The GMCH2-M provides refresh functionality
with programmable rate (normal DRAM rate is 1 refresh/15.6
μ
s). The GMCH2-M can be configured via
the Page Closing Policy Bit in the GMCH2-M Configuration Register to keep multiple pages open within
the memory array. Pages can be kept open in any one row of memory. Up to 4 pages can be kept open
within that row (The GMCH2-M only supports 4 Bank SDRAMs on system DRAM interface).
4.9.1.
DRAM Organization and Configuration
The GMCH2-M supports 64-bit SDRAM configurations. In the following discussion the term row
refers
to a set of memory devices that are simultaneously selected by a SCS# signal. The GMCH2-M will
support a maximum of 6 rows of memory.
The interface consists of the following pins:
Multiple copies:
SMAA[7:4], SMAB[7:4]# , SMAC[7:4]#
Single Copies:
SMD[63:0]
SDQM[7:0]
SMAA[12:8,3:0]
SBS[1:0]
SCSA[5:0]#
SCSB[5:0]#
SCAS#
SRAS#
SWE#
SCKE[5:0]
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