參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 143/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
143
Figure 9. Digital Video Out Port Mobile Application Block Diagram With VCH
815EM
Data [11:0]
FW82807AA
D
3rd Party TV Encoder
or Flat Panel Transmitter
or Combo Chip
DVOr signals
Figure 10. Digital Video Out Port Block Diagram Without VCH
Analog RGB
Monitor
Analog RGB
D
3rd Party
TV Encoder
or
Flat Panel Transmitter
or
Combo Chip
Digital (TMDS)
LCD or
Digital CRT
Differential Clock
Differential Data [11:0]
INTRPT#
815EM
NTSC/PAL
DVOrBlank#
DVOrVsync
DVOrHsync
DVOrCLKIN
DVOP Blk Diag
4.12.12.2. DVO Port Data Format
The Intel
DVO port data bus width is 12-bits wide, the data is output in a 12-bit package at each edge of
a pixel clock, and uses the LTVBLANK signal to determine when active pixel data is available.
Intel
DVO port overlay input data can be YUV progressive. In this case the overlay should be set to
frame mode. Each overlay buffer contains a frame, and the overlay is flipped between them. The overlay
does not do anything special, since the data matches the typical non-interlaced CRT screens. In other
cases, where the input data is an interlaced field type data, the overlay can be set to field mode, and
interlaced scanning is bi-linearly filtered into progressive data before it is displayed.
Connecting the GMCH2-M to a flat panel transmitter is demonstrated below. For more details, refer to
The
815EM Mobile Platform Recommended Design and Debug Practices
.
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