參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 39/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
39
3.4.
PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported
by a mapping mechanism implemented within the GMCH2-M.
The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and
Mechanism #2. The GMCH2-M supports only Mechanism #1.
The configuration access mechanism
makes use of the CONFIG_ADDRESS Register and CONFIG_DATA Register. To reference a
configuration register a Dword I/O write cycle is used to place a value into CONFIG_ADDRESS that
specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration
register of the device function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a
configuration cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space
specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in
the GMCH2-M translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The GMCH2-M is responsible for translating and routing the processor I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH2-M configuration registers, the
internal graphic device, or the hub interface.
3.5.
PCI Configuration Space Access
The GMCH2-M and the ICH2-M are physically connected via the hub interface. From a configuration
standpoint, the hub interface connecting the GMCH2-M and the ICH2-M is
logically PCI bus #0
. All
devices internal to the GMCH2-M and ICH2-M appear to be on PCI bus #0. The system primary PCI
expansion bus is physically attached to the ICH2-M and, from a configuration standpoint appears as a
hierarchical PCI bus behind a PCI-to-PCI bridge. The primary PCI expansion bus connected to the
ICH2-M has a programmable PCI Bus number.
The GMCH2-M contains three PCI devices within a single physical component. The configuration
registers for both Devices 0, 1 and 2 are mapped as devices residing on PCI bus #0.
Device 0:
Host-hub interface Bridge/DRAM Controller.
Device 1:
AGP Bridge supporting 1X/2X/4X transactions.
Device 2:
GMCH2-M internal graphics device (GFX).
Note:
Even though the primary PCI expansion bus is referred to as PCI0 in this document it is not PCI bus #0
from a configuration standpoint. Note that a physical PCI bus #0 does not exist. The hub interface and
the internal devices in the GMCH2-M and ICH2-M logically constitute PCI Bus #0 to configuration
software.
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