參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 30/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
30
Datasheet
2.5.
Hub Interface Signals
Signal Name
Type
Description
HL[10:0]
I/O
Hub Interface Signals:
Signals used for the hub interface.
HLSTRB
I/O
Packet Strobe:
One of two differential strobe signals used to transmit or receive
packet data.
HLSTRB#
I/O
Packet Strobe Compliment:
One of two differential strobe signals used to transmit
or receive packet data.
HLREF
I
Ref
HUB reference:
Sets the differential voltage reference for the hub interface.
2.6.
Display Interface Signals
Signal Name
Type
Description
VSYNC
O
3.3V
CRT Vertical Synchronization:
This signal is used as the vertical sync (polarity is
programmable) or “ Vsync Interval”.
HSYNC
O
3.3V
CRT Horizontal Synchronization:
This signal is used as the horizontal sync
(polarity is programmable) or “ Hsync Interval”.
IWASTE
I
Ref
Waste Reference:
This signal must be tied to ground.
IREF
I
Ref
Set pointer resistor for the internal color palette DAC.
A 174 ohm 1% resistor is
recommended
RED
O
Analog
CRT Analog video output from the internal color palette DAC:
The DAC is
designed for a 37.5 ohms equivalent load on each pin (e.g. 75 ohms resistor on the
board, in parallel with the 75 ohms CRT load)
GREEN
O
Analog
CRT Analog video output from the internal color palette DAC:
The DAC is
designed for a 37.5 ohms equivalent load on each pin (e.g. 75 ohms resistor on the
board, in parallel with the 75 ohms CRT load)
BLUE
O
Analog
CRT Analog video output from the internal color palette DAC:
The DAC is
designed for a 37.5 ohms equivalent load on each pin (e.g., 75 ohms resistor on the
board, in parallel with the 75 ohms CRT load)
DDCK
I/O
CMOS
CRT Monitor DDC Interface Clock:
(Also referred to as VESA
“Display Data
Channel”, also referred to as the “Monitor Plug-n-Play” interface.) For DDC1, DDCK
and DDDA provide a unidirectional channel for Extended Display ID. For DDC2,
DDCK and DDDA can be used to establish a bi-directional channel based on I
C
protocol. The host can request Extended Display ID or Video Display Interface
information over the DDC2 channel.
DDDA
I/O
CMOS
CRT Monitor DDC Interface Data:
See DDCK Description
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