參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 36/163頁
文件大?。?/td> 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
36
Datasheet
3.2.
GMCH2-M Register Introduction
The GMCH2-M contains two sets of software accessible registers, accessed via the Host I/O address
space:
I/O mapped Control registers in the host I/O space: These register controls the access to PCI
configuration space (see section entitled I/O Mapped Registers)
Internal GMCH2-M configuration registers: These are partitioned into three logical device register
sets (“l(fā)ogical” since they reside within a single physical device).
Device #0: Host-hub interface Bridge/DRAM Controller functionality controls PCI bus 0 such
as PCI registers, DRAM configuration, other chip-set operating parameters and optional
features.
Device #1: The second register block is dedicated to the AGP interface.
Device #2: The third block is dedicated to the internal graphics device (GFX) in the GMCH2-
M.
The GMCH2-M supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification. The GMCH2-M internal registers (both I/O
Mapped and Configuration registers) are accessible by the host. The registers can be accessed as Byte,
Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only
be accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses
contain the least significant parts of the field).
3.3.
I/O Mapped Registers
The GMCH2-M contains two registers that reside in the processor I/O address space
Configuration Address Register (CONFIG_ADDRESS):
CONFIG_ADDRESS is a 32 bit register accessed only when referenced as a Dword. A Byte or
Word reference will "pass through" the Configuration Address Register onto the PCI0 bus as an
I/O cycle. The CONFIG_ADDRESS register contains the PCI Bus Number, PCI Device
Number, PCI Function Number, and PCI Register Number for which a subsequent configuration
access is intended. The register numbers, bit 7:2 in CONFIG_ADDRESS, is the upper 6 bits of
the dword-aligned byte offset address of the selected dword.
Configuration Data Register (CONFIG_DATA):
CONFIG_DATA is a 32 bit Read/Write window into the specified dword of the pCI
configuration space selected by CONFIG_ADDRESS. The portion of configuration space that is
referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Reads
and writes to the PCI Configuration space can be byte, word, or dword, via I/O read or write
instructions to the CONFIG_DATA port.
The Configuration Address Register enables/disables the configuration space and determines what
portion of configuration space is visible through the Configuration Data window.
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