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| 型號(hào)： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 147/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
147
4.15.1.
Specifications Supported
The platform is compliant with the following specifications:
APM Rev 1.2
ACPI Rev 1.0
PCI Power Management Rev 1.0
PC 99 System Design Guide, Rev 1.0
This chapter includes general description of the ACPI power states, transition rules among its states,
power states Intel
815EM chipset supports, entering and exiting C2/C3/S1/S3 state. Intel
815EM
chipset supports several levels of power management.
4.16.
General Description of ACPI Power States
Intel
815EM chipset will support the ACPI compliant power states. The following table describes in
general the ACPI power states. It is for informational purposes and should not be used by designers or
validations as part of the behavioral description.
Table 24. General Description of ACPI Power States
G0/S0/C0
Full on: Processor is fully operating. Individual devices may be shutdown to save power.
Different processor operating levels are described in system level state transition table
below. Within the C0 state, the ICH2-M can throttle the STPCLK# signal to further reduce
power consumption.
G0/S0/C1
Auto-Halt: Processor has executed an AutoHalt instruction and is not executing code. The
processor snoops the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant for Desktop or Quick-start for Mobile: The STPCLK# signal goes active to the
processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and
remain in that state until the STPCLK# signal goes inactive. In the Stop-Grant state, the
processor snoops the bus and maintains cache coherency. The Quick-start state is lower
power version, but there are restrictions on what interrupt signals can go active while
STPCLK# is active. Note: Some mobile systems may use the Stop-Grant state rather than
the Quick-start state.
G0/S0/C3
Stop-Clock: This is only for mobile systems. The STPCLK# signal goes active to the
processor. The processor performs a Stop-Grant cycle and halts its instruction stream.
ICH2-M then asserts STP_CPU# that forces the clock generator to stop the processor
clock. This is also used in the mobile system for Intel
SpeedStep
Technology support.
G1/S1(Desktop)
Stop-Grant: Similar to G0/S0/C2 state. ICH2-M also has the option to assert CPUSLP#
signal to the processor to further reduce power consumption.
G1/S1 (Mobile)
Power-On Suspend (POS): In this state, all clocks are stopped except the 32.768 KHz
clock. The system context is maintained in the system memory. Power is on to processor,
PCI, memory controller, memory, and all other critical circuits.
G1/S3
Suspend-to-RAM (STR): The system context is maintained in system memory, but power
is shut to non-critical circuits. Memory is retained and refreshes continue. All clocks are
shut except RTC.
G1/S4
Suspend-to-Disk (STD): The system context is maintained on the disk. All power is shut
except for the logic required to resume. Externally appears same as S5, but may have
different wake events.
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