參數資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數據表參考
文件頁數： 120/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
120
Datasheet
4.4.3.
SMM Space Combinations
When HSEG SMM is enabled, the Compatible SMM space must be disabled. Processor originated
accesses to the Compatible SMM space are forwarded to AGP if VGAEN=1 (also depends on MDAP),
otherwise they are forwarded to the hub interface. AGP and the hub interface originated accesses are
never
allowed to access SMM space. Only the processor is allowed to access SMM space. AGP and hub
interface originated transactions are not allowed to SMM space.
4.4.4.
Initialization and Usage of SMRAM and Graphics Local Memory
SMRAM Register Bits 7:4 control the usage of memory from Main Memory space for use as Graphics
Local Memory and SMM TSEG memory. The blocks of memory selected by these fields are NOT
accessible as general system RAM. When Bit 5 of the SMRAM register is a “1” the TSEG segment of
memory can ONLY be accessed by the processor in SMM mode (No other agent can access this
memory). Therefore, BIOS should initialize this block of memory BEFORE setting either Bit 5 or Bit 7
of the SMRAM register. The memory for TSEG is used first and then the Graphics Local Memory is
used. An example of this memory usage mechanism is:
TOM equal 64 MB,
TSEG selected as 512 KB in size,
Graphics Local Memory selected as 1 MB in size
General System RAM available in system = 62.5 MB
General System RAM Range
TSEG Address Range
TSEG used from
Graphics Local Memory used from
00000000h to 03E7FFFFh
03F80000h to 03FFFFFFh
03F80000h to 03FFFFFFh
03E80000h to 03F7FFFFh
4.5.
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into
GMCH2-M DRAM memory. Typically this is done to allow ROM code to execute more rapidly out of
main DRAM. ROM is used as a read-only during the copy process while DRAM at the same time is
designated write-only. After copying, the DRAM is designated read-only so that ROM is shadowed.
processor bus transactions are routed accordingly.
4.6.
I/O Address Space
The GMCH2-M does not support the existence of any other I/O devices other than itself on the processor
bus. The GMCH2-M generates either hub interface or AGP/PCI (if enabled) bus cycles for all processor
I/O accesses. If internal graphics is enabled, the GMCH2-M routes the access to hub interface or legacy
I/O registers supported by the internal Graphics Device.
The GMCH2-M contains two internal registers in the processor I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). These
locations are used to implement PCI configuration space access mechanism and as described in
chapter 3.
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