參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 65/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
65
3.6.25.
BUFF_SC—System Memory Buffer Strength Control Register
(Device 0)
Address Offset:
92-93h
Default Value:
FFFFh
Access:
Read/Write
Size:
16 bits
This register programs the system memory DRAM interface signal buffer strengths, with the exception of
the CKEs. The programming of these bits should be based on DRAM density (x8 or x16), DRAM
technology (16Mb, 64Mb, 128Mb or 256 Mb), rows populated, etc. Note that x4 & x32 DRAMs are not
supported. Registered DIMMs and DIMMS with ECC are also not supported and BIOS upon detection
of ECC via SPD, should report to the user that ECC DIMM timings are not supported by the GMCH2-M.
Note SO-DIMM only support x16 DRAM density.
In the descriptions below, the term “Row” is equivalent to one side of one DIMM. In other words, a
“single-sided” DIMM contains one populated row (always an odd numbered), and one empty row (even
numbered). A “double-sided” DIMM contains two populated rows.
All buffer strengths are based on the number of “l(fā)oads” connected to each pin of a given signal group. A
“l(fā)oad” represents one pin of one SDRAM Device. The GMCH2-M pin is implied and not counted in the
load equations. The number of loads on a given signal for a given configuration can be determined
entirely from the width of the SDRAM devices that populate each row in the configuration. This
information is readily available for each row via the Serial Presence Detect mechanism.
15
14
13
12
11
10
9
8
SCS[5]#
Buffer
Strength
SCS[4]#
Buffer
Strength
SCS[3]#
Buffer
Strength
SCS[2]#
Buffer
Strength
SCS[1]#
Buffer
Strength
SCS[0]#
Buffer
Strength
SMAC[7:4]# Buffer
Strength
7
6
5
4
3
2
1
0
SMAB[7:4]# Buffer
Strength
SMAA[7:4] Buffer
Strength
SMD and SDQM Buffer
Strengths
Control Buffer Strengths
Bit
Description
15
SCS[5]# Buffer Strength (Row 5).
0 = 1.7x 4 loads
1 = 1.0x 0 or 2 loads
Each Row is actually selected by a pair of Chip Select signals (SCSA[n]# and SCSB[n]#).
The number of SCS# loads for a given Row can be determined from SPD data using the following
equation:
Loads = 32 / (width of SDRAM devices in row)
14
SCS[4]# Buffer Strength (Row 4).
0 = 1.7x 4 loads
1 = 1.0x 0 or 2 loads
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