參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 129/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
129
The GMCH2-M supports SO-DIMMs with 16 bit wide SDRAM devices. Registered DIMMs or DIMMs
populated with 4 bit wide SDRAM devices are not supported. The GMCH2-M supports 3.3v standard
SDRAMs.
4.9.1.1.
Configuration Mechanism SO-DIMMs
Detection of the type of DRAM installed on the SO-DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM standard and 144-pin SO-DIMM standard. This
standard uses the SCL, SDA and SA[2:0] pins on the SO-DIMMs to detect the type and size of the
installed SO-DIMMs. No special programmable modes are provided on the GMCH2-M for detecting the
size and type of memory installed. Type and size detection must be done via the serial presence detection
pins. Use of Serial Presence Detection is required.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the GMCH2-M DRAM registers must be
initialized. The GMCH2-M must be configured for operation with the installed memory types. Detection
of memory type and size is done via the System Management Bus (SMBus) interface on the ICH2-M.
This two wire bus is used to extract the DRAM type and size information from the serial presence detect
port on the DRAM SO-DIMM modules.
4.9.1.2.
DRAM Register Programming
This section provides an overview of how the required information for programming the DRAM registers
is obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence Detect ports
are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis),
SDRAM Timings, Row Sizes and Row Page Sizes.
The following Table 5-6 lists a subset of the data available through the on-board Serial Presence Detect
ROM on each SO-DIMM module.
Table 15. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
Function
2
Memory Type (EDO, SDRAM) the GMCH2-M only supports SDRAM.
3
# of Row Addresses, not counting Bank Addresses
4
# of Column Addresses
5
# of banks of DRAM (Single or Double sided) DIMM
12
Refresh Rate
17
# Banks on each SDRAM Device
36-41
Access Time from Clock for CAS# Latency 1 through 7
42
Data Width of SDRAM Components
These bytes collectively provide enough data for BIOS to program the GMCH2-M DRAM registers.
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