參數(shù)資料
型號: L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達(dá)驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 84/103頁
文件大?。?/td> 853K
代理商: L9805
84/103
L9805
Figure 45. EEPROM Programming Flowchart
5.9.3 Register Description
EEPROM CONTROL REGISTER (EECR)
Address: 002Ch - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 =
E2ITE
: Interrupt enable.
This bit is set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled
When the programming cycle is finished (E2PGM
toggle from 1 to 0), an interrupt is generated only if
E2ITE is high. The interrupt is automatically
cleared when the micro-controller enters the EEP-
ROM interrupt routine.
Bit 1 =
E2LAT
: Read/Write mode.
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
be cleared by software only if E2PGM=0.
0: Read mode
1: Write mode
When E2LAT=1, if the E2PGM bit is low and the
micro-controller is in write mode, the 8 bit data bus
is stored in one of the four groups of 8 bit data
latches, selected by the address. This happens
every time the device executes an EEPROM Write
instruction. If E2PGM remains low, the content of
the 8 bit data latches is not transferred into the ma-
trix, because the High Voltage charge-pump does
not start. The 8 data latches are selected by the
lower part of the address (A<1:0> bits). If 4 con-
secutive write instructions are executed, by
sweeping from A<1:0>=0h to A<1:0>=3h, with the
E2LAT=1
E2PGM=0
(Write mode)
Write bytes in
EEPROM
E2LAT=1
E2PGM=1
(Start
programming
cycle)
Wait for end of
programming
(E2LAT=0
or interrupt)
Write 1 to 4 bytes in
the same row (with
the same 12 Most
Significant Bits of
the address)
E2LAT=0
E2PGM=0
(Read mode)
7
0
0
0
0
0
0
E2ITE
E2LAT
E2PGM
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