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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導體 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達驅動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵 |
| 文件頁數(shù)： | 40/103頁 |
| 文件大?。?/td> | 853K |
| 代理商： | L9805 |
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40/103
L9805
16-BIT TIMER
(Cont’d)
5.2.3.5 Forced Compare Mode
In this section imay represent 1 or 2.
The main purpose of the Forced Compare mode is
to easily generate a fixed frequency.
The following bits of the CR1 register are used:
When the FOLVibit is set, the OLVLibit is copied
to the OCMPi pin.
To provide this capability, internal logic allows a
single instruction to change the OLVLibit and
causes a forced compare with the new value of the
OLVLi bit.
The OCFibit is not set, and thus no interrupt re-
quest is generated.
5.2.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
– Set OC1E pin, the OCMP1 pin is then dedicated
to the Output Compare 1 function.
And select the following in the CR2 register:
– Set the OPM bit.
– Select the timer clock CC1-CC0 (see
Table 7
Clock Control Bits
).
Load the OCR1 register with the value corre-
sponding to the length of the pulse (see the formu-
la in
Section 5.2.3.7
).
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OCR1
register, the OLVL1 bit is output on the OCMP1
pin, (See
Figure 24
).
Note:
The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 24.
One
Pulse Mode Timing
FOLV
2
FOLV
1
OLVL
2
OLVL
1
event occurs
on ICAP1
Counter is
initialized
to FFFCh
OCMP1 = OLVL2
Counter
= OCR1
OCMP1 = OLVL1
When
When
One pulse mode cycle
COUNTER
....
FFFC FFFD FFFE
2ED0
2ED1 2ED2
2ED3
FFFC FFFD
OLVL2
OLVL2
OLVL1
ICAP1
OCMP1
compare1
Note:
IEDG1=1, OCR1=2ED0h, OLVL1=0, OLVL2=1
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