參數(shù)資料
型號: L9805
廠商: 意法半導體
元件分類: 基準電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 45/103頁
文件大?。?/td> 853K
代理商: L9805
45/103
L9805
16-BIT TIMER
(Cont’d)
STATUS REGISTER (SR)
Timer1 Register Address: 0033h
Timer2 Register Address: 0043h
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
Bit 7 =
ICF1
Input Capture Flag 1.
0: No input capture (reset value)
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the ICR1 (ICLR1) register.
Bit 6 =
OCF1
Output Compare Flag 1.
0: No match (reset value)
1: The content of the free running counter has
matched the content of the OCR1 register. To
clear this bit, first read the SR register, then read
or write the low byte of the OCR1 (OCLR1) reg-
ister.
Bit 5 =
TOF
Timer Overflow.
0: No timer overflow (reset value)
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Note:
Reading or writing the ACLR register do not
clear TOF.
Bit 4 =
ICF2
Input Capture Flag 2.
0: No input capture (reset value)
1: An input capture has occurred.To clear this bit,
first read the SR register, then read or write the
low byte of the ICR2 (ICLR2) register.
Bit 3 =
OCF2
Output Compare Flag 2.
0: No match (reset value)
1: The content of the free running counter has
matched the content of the OCR2 register. To
clear this bit, first read the SR register, then read
or write the low byte of the OCR2 (OCLR2) reg-
ister.
Bit 2-0 = Unused.
0
ICF1
OCF1
TOF
ICF2
OCF2
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相關代理商/技術參數(shù)
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