參數(shù)資料
型號： L9805
廠商： 意法半導(dǎo)體
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述： 超級智能型電動馬達(dá)驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵
文件頁數(shù)： 77/103頁
文件大?。?/td> 853K
代理商： L9805
77/103
L9805
5.8 POWER BRIDGE
5.8.1 Introduction
The power part of the device consists of two iden-
tical independent DMOS half bridges. It is suited to
drive resistive and inductive loads.
5.8.2 Main Features
The Rdson of each of the 4 DMOS transistors is 60
m
at 25°C.
The nominal current is 2A.
The maximum current is 5A.
The low-side switch is a n-channel DMOS transis-
tor while the high-side switch is a p-channel
DMOS transistor. Therefore no charge pump is
needed.
An anti-crossconduction circuit is included: the low
side DMOS is switched on only when the high side
is switched off and vice versa. This function avoid
the two DMOS are switched on together firing the
high current path from battery to ground. The func-
tion is obtained by sensing the gate voltage and
therefore the delay between command and effec-
tive switch on of the DMOS doesn’t have a fixed
length.
The MCU controls all operations of the power
stage through the BCSR dedicated register. Short
circuit and overtemperature conditions are report-
ed to the CPU using dedicated error flags.
Overtemperature and short circuit conditions
switch off the bridge immediately without CPU in-
tervention. The function of the flags is independent
of the operation mode of the bridge (sink, source,
Z).
In addition both the PWM modules can be directly
connected to the power bridge. The power bridge
offers then many driving mode alternatives:
Direct Mode: the two half bridges are directly driv-
en by IN1 and IN2 control bit in BCSR.
PWM1 Up/Down Brake Mode: the output of PWM1
drives one side of the bridge while the other side is
maintained in a fixed status.
PWM1 Symmetrical Driving Mode: PWM1 line
drives directly and symmetrically both side of the
bridge.
PWM1/PWM2 Mode: PWM1 drives one side while
PWM2 drives the other (two independent half
bridges).
5.8.3 Functional Description
A schematic description of the Power Bridge cir-
cuit is depicted in
Figure 41
. In this schematic the
transistors must be considered in ON condition
when they gate is high (set).
Figure 41. Power Bridge Schematic
EN bit in BCSR is the main enable signal, active
high. If EN = 0, all the bridge transistors are
switched off (UL, UR, DL and DR are reset) and
the outputs OUTL and OUTR are in high imped-
ance state.
Being '0' the status after reset of EN, the bridge is
in safe condition (OUTL=OUTR=Z). Therefore the
VBR
PGND
OUTR
VBL
PGND
OUTL
UL
UR
DL
DR
SC_UL
OVT
SC_DL
OVT
SC_DR
OVT
SC_UR
OVT
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