參數(shù)資料
型號: L9805
廠商: 意法半導體
元件分類: 基準電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 13/103頁
文件大?。?/td> 853K
代理商: L9805
13/103
L9805
CPU REGISTERS
(Cont’d)
Stack Pointer (SP)
The Stack Pointer is a 16-bit
register. Since the stack is 64 bytes deep, the
most significant bits are forced as indicated in
Figure 2, on page 12 in order to address the stack
as it is mapped in memory.
Following an MCU Reset, or after a Reset Stack
Pointer instruction (RSP), the Stack Pointer is set
to point to the next free location in the stack. It is
then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack.
Note:
When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost.
The upper and lower limits of the stack area are
shown in the Memory Map.
The stack is used to save the CPU context during
subroutine calls or interrupts. The user may also
directly manipulate the stack by means of the
PUSH and POP instructions. In the case of an in-
terrupt (refer to
Figure 3
), the PCL is stored at the
first location pointed to by the SP. Then the other
registers are stored in the next locations.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Condition Code Register (CC)
The Condition
Code register is a 5-bit register which indicates the
result of the instruction just executed as well as the
state of the processor. These bits can be individu-
ally tested by a program and specified action taken
as a result of their state. The following paragraphs
describe each bit of the CC register in turn.
Half carry bit (H)
The H bit is set to 1 when a carry
occurs between bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H bit is useful in BCD
arithmetic subroutines.
Interrupt mask (I)
When the I bit is set to 1, all in-
terrupts except the TRAP software interrupt are
disabled. Clearing this bit enables interrupts to be
passed to the processor core. Interrupts requested
while I is set are latched and can be processed
when I is cleared (only one interrupt request per in-
terrupt enable flag can be latched).
Negative (N)
When set to 1, this bit indicates that
the result of the last arithmetic, logical or data ma-
nipulation is negative (i.e. the most significant bit is
a logic 1).
Zero (Z)
When set to 1, this bit indicates that the
result of the last arithmetic, logical or data manipu-
lation is zero.
Carry/Borrow (C)
When set, C indicates that a
carry or borrow out of the ALU occured during the
last arithmetic operation. This bit is also affected
during execution of bit test, branch, shift, rotate
and store instructions.
Figure 3. Stack Manipulation on Interrupt
CONDITION CODE
ACCUMULATOR
X INDEX REGISTER
PCH
PCL
1
1
1
0
7
HIGHER ADDRESS
LOWER ADDRESS
CONTEXT RESTORED
ON RETURN
CONTEXT SAVED
ON INTERRUPT
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