參數(shù)資料
型號: L9805
廠商: 意法半導(dǎo)體
元件分類: 基準電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 68/103頁
文件大?。?/td> 853K
代理商: L9805
68/103
L9805
CONTROLLER AREA NETWORK
(Cont’d)
CONTROL/STATUS REGISTER (CSR)
Address: 005Ch - Read/Write
Reset Value: 00h
BOFF
Bus-Off State
Read Only
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds
255.
Reset by hardware to indicate that the node is in-
volved in bus activities.
EPSV
Error Passive State
Read Only
Set by hardware to indicate that the node is error
passive.
Reset by hardware to indicate that the node is either
error active (BOFF = 0) or bus-off.
Bit 4 =
SRTE
Simultaneous Receive/Transmit En-
able
Read/Set/Clear
Set by software to enable simultaneous transmis-
sion and reception of a message passing the ac-
ceptance filtering. Allows to check the integrity of
the communication path.
Reset by software to discard all messages trans-
mitted by the node. Allows remote and data frames
to share the same identifier.
NRTX
No Retransmission
Read/Set/Clear
Set by software to disable the retransmission of un-
successful messages.
Cleared by software to enable retransmission of
messages until success is met.
FSYN
Fast Synchronization
Read/Set/Clear
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait for only 11 re-
cessive bits in a row.
Cleared by software to enable the standard resyn-
chronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
WKPS
Wake-up Pulse
Read/Set/Clear
Set by software to generate a dominant pulse when
leaving standby mode.
Cleared by software for no dominant wake-up
pulse.
RUN
CAN Enable
Read/Set/Clear
Set by software to leave stand-by mode after 128
sequences of 11 recessive bits or just 11 recessive
bits if FSYN is set.
Cleared by software to request a switch to the
stand-by or low-power mode as soon as any on-go-
ing transfer is complete. Read-back as 1 in the
meantime to enable proper signalling of the stand-
by state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.
7
0
0
BOFF
EPSV
SRTE
NRTX
FSYN WKPS
RUN
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