參數(shù)資料
型號(hào): L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級(jí)智能型電動(dòng)馬達(dá)驅(qū)動(dòng)器,帶有8位微控制器,CAN接口,16K的存儲(chǔ)器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時(shí)器,2個(gè)PWM模塊,涪陵
文件頁(yè)數(shù): 43/103頁(yè)
文件大?。?/td> 853K
代理商: L9805
43/103
L9805
16-BIT TIMER
(Cont’d)
5.2.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
CONTROL REGISTER 1 (CR1)
Timer1 Register Address: 0032h
Timer2 Register Address: 0042h
Read/Write
Reset Value: 0000 0000 (00h)
7
Bit 7 =
ICIE
Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bits of the SR register are set
Bit 6 =
OCIE
Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bits of the SR register are set
Bit 5 =
TOIE
Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 4 =
FOLV2
Forced Output Compare 2.
0: No effect.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin.
Bit 3 =
FOLV1
Forced Output Compare 1.
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1 pin.
Bit 2 =
OLVL2
Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OCR2 reg-
ister. This value is copied to the OCMP1 pin in
One Pulse Mode and Pulse Width Modulation
mode.
Bit 1 =
IEDG1
Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
OLVL1
Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OCR1 register.
0
ICIE OCIE TOIE
FOLV
2
FOLV
1
OLVL
2
IEDG
1
OLVL
1
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