參數(shù)資料
型號(hào)： L9805
廠商： 意法半導(dǎo)體
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述： 超級(jí)智能型電動(dòng)馬達(dá)驅(qū)動(dòng)器，帶有8位微控制器，CAN接口，16K的存儲(chǔ)器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時(shí)器，2個(gè)PWM模塊，涪陵
文件頁數(shù)： 20/103頁
文件大?。?/td> 853K
代理商： L9805
20/103
L9805
3.5 RESET
3.5.1 Introduction
There are four sources of Reset:
– NRESET pin (external source)
– Power-On Reset / Low Voltage Detection (Inter-
nal source)
– WATCHDOG (Internal Source)
– SAFEGUARD (Internal source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.5.2 External Reset
The NRESET pin is both an input and an open-
drain output with integrated pull-up resistor. When
one of the internal Reset sources is active, the Re-
set pin is driven low to reset the whole application.
3.5.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The NRESET pin may thus be
used to ensure V
DD
has risen to a point where the
MCU can operate correctly before the user pro-
gram is run. Following a Power-On Reset event, or
after exiting Halt mode, a 4096 CPU Clock cycle
delay period is initiated in order to allow the oscil-
lator to stabilise and to ensure that recovery has
taken place from the Reset state.
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low. In its high state, an
internal pull-up resistor of about 300K
is con-
nected to the Reset pin. This resistor can be pulled
low by external circuitry to reset the device.
3.5.4 Power-on Reset - Low Voltage Detection
The POR/LVD function generates a static reset
when the supply voltage is below a reference val-
ue. In this way, the Power-On Reset and Low Volt-
age Reset function are provided, in order to keep
the system in safe condition when the voltage is
too low.
The Power-Up and Power-Down thresholds are
different, in order to avoid spurious reset when the
MCU starts running and sinks current from the
supply.
The LVD reset circuitry generates a reset when
V
DD
is below:
– V
ResetON
when V
DD
is rising
– V
ResetOFF
when V
DD
is falling
The POR/LVD function is explained in
Figure 9
.
Power-On Reset activates the reset pull up tran-
sistor performing a complete chip reset. In the
same way a reset can be triggered by the watch-
dog, by the safeguard or by external low level at
NRESET pin. An external capacitor connected be-
tween NRESET and ground can extend the power
on reset period if required.
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