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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達(dá)驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時(shí)器，2個(gè)PWM模塊，涪陵 |
| 文件頁數(shù)： | 44/103頁 |
| 文件大?。?/td> | 853K |
| 代理商： | L9805 |
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44/103
L9805
16-BIT TIMER
(Cont’d)
CONTROL REGISTER 2 (CR2)
Timer1 Register Address: 0031h
Timer2 Register Address: 0041h
Read/Write
Reset Value: 0000 0000 (00h)
7
Bit 7 =
OC1E
Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but the
OCMP1 pin is a general I/O.
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
Bit 6 =
OC2E
Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
OCMP2 pin is a general I/O.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
Bit 5 =
OPM
One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OCR1 register.
Bit 4 =
PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OCR1 register;
the period depends on the value of OCR2 regis-
ter.
Bit 3, 2 =
CC1-CC0
Clock Control.
The value of the timer clock depends on these bits:
Table 7. Clock Control Bits
Bit 1 =
IEDG2
Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
EXEDG
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
CC1
CC0
Timer Clock
0
0
1
0
1
0
f
CPU
/ 4
f
CPU
/ 2
f
CPU
/ 8
1
1
External Clock (where
available)
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