參數(shù)資料
型號(hào)： L9805
廠商： 意法半導(dǎo)體
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述： 超級(jí)智能型電動(dòng)馬達(dá)驅(qū)動(dòng)器，帶有8位微控制器，CAN接口，16K的存儲(chǔ)器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時(shí)器，2個(gè)PWM模塊，涪陵
文件頁(yè)數(shù)： 56/103頁(yè)
文件大小： 853K
代理商： L9805
56/103
L9805
5.5 10-BIT A/D CONVERTER (AD10)
5.5.1 Introduction
The Analog to Digital converter is a single 10-bit
successive approximation converter with 4 input
channels. Analog voltage from external sources
are input to the converter through AD2,AD3 and
AD4 pins. Channel 1 (AD1) is connected to the in-
ternal temperature sensor (see
Section 5.5.5
).
Note
The anti aliasing filtering must be accom-
plished using an external RC filter. The internal
AD1 channel is filtered by an RC network with ap-
prox. 1us time constant.
5.5.2 Functional Description
The result of the conversion is stored in 2 regis-
ters: the Data Register High (ADCDRH) and the
Data Register Low (ADCDRL).
The A/D converter is enabled by setting the ADST
bit in ADCCSR Register. Bits CH1 and CH0 of AD-
CCSR Register select the channel to be convert-
ed. The high and low reference voltage are con-
nected to pins VCC and AGND.
When enabled, the A/D converter performs a com-
plete conversion in 14us (with system clock
f
CPU
=8Mhz). The total conversion time includes
multiplex, sampling of the input voltage, 10-bit
conversion and writing DRH and DRL registers.
When the conversion is completed COCO bit
(COnversion COmpleted) is set in ADCCSR.
A conversion starts from the moment ADST bit is
set. When a conversion is running it is possible to
write the ADCCSR without stopping the ADC oper-
ations, because all the data in ADCCSR are
latched when ADST is set. This property allows to
select a different channel to be processed during
the next conversion or to manage the interrupt en-
able bit. The new setting will have effect on the
next conversion (including interrupt generation)
At the end of the conversion ADST is reset and
COCO bit is set.
Note
To start a new conversion the ADST must be
set after the completion of the current one. Any
writing to ADST when a conversion is running
(COCO=0) has no effect since ADST bit is auto-
matically reset by the end of conversion event.
Figure 32. Block diagram of the Analog to Digital Converter
CH0
CH1
ADST
logic
U
X
M
d
i
v
clk
8Mhz
2 Mhz
start conversion
end conversion
.....
AD0
AD9
DRH
DRL
WR
Vin
VCC
AGND
inputs
CSR
sampling
+
conversion
latch
ADIE
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