參數(shù)資料
型號： L9805
廠商： 意法半導(dǎo)體
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述： 超級智能型電動馬達(dá)驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵
文件頁數(shù)： 66/103頁
文件大?。?/td> 853K
代理商： L9805
66/103
L9805
CONTROLLER AREA NETWORK
(Cont’d)
5.6.4 Register Description
The CAN registers are organized as 6 general pur-
pose registers plus 5 pages of 16 registers span-
ning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Se-
lection Register. Refer to
Figure 38
.
5.6.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Address: 005Ah - Read/Write
Reset Value: 00h
RXIF3
Receive Interrupt Flag for Buffer 3
Read/Clear
Set by hardware to signal that a new error-free mes-
sage is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
RXIF2
Receive Interrupt Flag for Buffer 2
Read/Clear
Set by hardware to signal that a new error-free
message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
RXIF1
Receive Interrupt Flag for Buffer 1
Read/Clear
Set by hardware to signal that a new error-free mes-
sage is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
TXIF
Transmit Interrupt Flag
Read/Clear
Set by hardware to signal that the highest priority
message queued for transmission has been suc-
cessfully transmitted (ETX = 0) or that it has passed
successfully the arbitration (ETX = 1).
Cleared by software.
SCIF
Status Change Interrupt Flag
Read/Clear
Set by hardware to signal the reception of a domi-
nant bit while in standby or a change from error ac-
tive to error passive and bus-off while in run. Also
signals any receive error when ESCI = 1.
Cleared by software.
ORIF
Overrun Interrupt Flag
Read/Clear
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
TEIF
Transmit Error Interrupt Flag
Read/Clear
Set by hardware to signal that an error occurred dur-
ing the transmission of the highest priority message
queued for transmission.
Cleared by software.
EPND
Error Interrupt Pending
Read Only
Set by hardware when at least one of the three error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Caution
;
Interrupt flags are reset by writing a "0" to the cor-
responding bit position. The appropriate way con-
sists in writing an immediate mask or the one’s com-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modify-
write nature.
7
0
RXIF3 RXIF2 RXIF1
TXIF
SCIF
ORIF
TEIF
EPND
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