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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達(dá)驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵 |
| 文件頁數(shù)： | 36/103頁 |
| 文件大小： | 853K |
| 代理商： | L9805 |
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36/103
L9805
16-BIT TIMER
(Cont’d)
5.2.3.3 Input Capture
In this section, the index, i may be 1 or 2
The two input capture 16-bit registers (ICR1 and
ICR2) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPipin (see figure 5).
ICRiregister is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (
f
CPU/(CC1.CC0)
).
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC1-CC0) (see
Table 7
Clock Control Bits
).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
– ICFibit is set.
– The ICRiregister contains the value of the free
running counter on the active transition on the
ICAPi pin (see
Figure 21
).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CCR register. Oth-
erwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICFibit is set.
2. An access (read or write) to the ICLRi egister.
Note:
After reading the ICHRiregister, transfer of
input capture data is inhibited until the ICLRiregis-
ter is also read.
The ICRiregister always contains the free running
counter value which corresponds to the most re-
cent input capture.
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAPipin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not “wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will become active, and data corre-
sponding to the first valid edge during HALT mode
will be present.
MS Byte
ICHRi
LS Byte
ICLRi
ICRi
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