參數(shù)資料
型號(hào)： L9805
廠商： 意法半導(dǎo)體
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述： 超級(jí)智能型電動(dòng)馬達(dá)驅(qū)動(dòng)器，帶有8位微控制器，CAN接口，16K的存儲(chǔ)器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時(shí)器，2個(gè)PWM模塊，涪陵
文件頁(yè)數(shù)： 41/103頁(yè)
文件大?。?/td> 853K
代理商： L9805
41/103
L9805
16-BIT TIMER
(Cont’d)
5.2.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OCR1 and OCR2
registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OCR2
register.
Procedure
To use pulse width modulation mode select the fol-
lowing in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OCR1 register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OCR2 register.
– Set OC1E bit: the OCMP1 pin is then dedicated
to the output compare 1 function.
And select the following in the CR2 register:
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see
Table 7
Clock Control Bits
).
Load the OCR2 register with the value corre-
sponding to the period of the signal.
Load the OCR1 register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OCR2 and OCR1
registers.
The OCRi register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
– t = Desired output compare period (seconds)
– f
CPU
= Internal clock frequency (see Miscella-
neous register)
– CC1-CC0 = Timer clock prescaler
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 25, on
page 42).
Note:
After a write instruction to the OCHRiregis-
ter, the output compare function is inhibited until
the OCLRi register is also written.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited. The Input Capture interrupt is
available.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
OCRiValue =
t
*
f
CPU
(CC1.CC0)
- 5
Counter
= OCR1
Counter is reset
to FFFCh
OCMP1 = OLVL2
Counter
= OCR2
OCMP1 = OLVL1
When
When
Pulse Width Modulation cycle
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