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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導體 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵 |
| 文件頁數(shù)： | 34/103頁 |
| 文件大?。?/td> | 853K |
| 代理商： | L9805 |
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L9805
16-BIT TIMER
(Cont’d)
16-bit read sequence:
(from either the Counter
Register or the Alternate Counter Register).
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1register is set and
– I bit of the CCR register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done by:
1. Reading the SR register while the TOF bit is
set.
2. An access (read or write) to the CLR register.
Notes:
The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
5.2.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXCLK
that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thus the external clock frequen-
cy must be less than a quarter of the CPU clock
frequency.
LSB is buffered
Read MSB
At t0
Read LSB
Returns the buffered
LSB value at
t0
At t0 +
t
Other
instructions
Beginning of the sequence
Sequence completed
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| L9805E | 功能描述:馬達/運動/點火控制器和驅(qū)動器 Super Smart Power 8-Bit MCU, RAM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Stepper Motor Controllers / Drivers 類型:2 Phase Stepper Motor Driver 工作電源電壓:8 V to 45 V 電源電流:0.5 mA 工作溫度:- 25 C to + 125 C 安裝風格:SMD/SMT 封裝 / 箱體:HTSSOP-28 封裝:Tube |
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| L9813 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SUPER SMART MIRROR WITH EMBEDDED MCU |
| L981CG-1 | 制造商:Thomas & Betts 功能描述:1/2 T CONDUIT BODY W/CVR & GASKET,E |
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