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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導體 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵 |
| 文件頁數(shù)： | 38/103頁 |
| 文件大小： | 853K |
| 代理商： | L9805 |
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38/103
L9805
16-BIT TIMER
(Cont’d)
5.2.3.4 Output Compare
In this section, the index, i may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OCR1) and Output Compare Register 2 (OCR2)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCRi value to 8000h.
Timing resolution is one count of the free running
counter: (
f
CPU/(CC1.CC0)
).
Procedure
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPipin is dedicated to the output compare i
function.
– Select the timer clock (CC1-CC0) (see
Table 7
Clock Control Bits
).
And select the following in the CR1 register:
– Select the OLVLibit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When match is found:
– OCFi bit is set.
– The OCMPipin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CCR register (CCR).
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCFi bit is
set.
4. An access (read or write) to the OCLRi register.
Note:
After a processor write cycle to the OCHRi
register, the output compare function is inhibited
until the OCLRi register is also written.
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
The value in the 16-bit OCRi egister and the OLVi
bit should be changed after each successful com-
parison in order to control an output waveform or
establish a new elapsed timeout.
The OCRiregister value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
OCRi register Value =
Where:
t
= Desired output compare period (in
seconds calculated from the current
counter)
= Internal clock frequency (see Miscel-
laneous register)
CC1-CC0 = Timer clock prescaler
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCRi register:
– Write to the OCHRiregister (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCLRiregister (enables the output
compare function and clears the OCFi bit).
f
CPU
MS Byte
OCHRi
LS Byte
OCLRi
OCRi
t
*
f
CPU
(CC1.CC0)
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