參數(shù)資料
型號: L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達(dá)驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 25/103頁
文件大?。?/td> 853K
代理商: L9805
25/103
L9805
POWER SAVING MODES
(Cont’d)
3.7.4 Halt Mode
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
either an external interrupt (I0), a internal interrupt
coming from the CAN peripheral (I1) or a reset.
The oscillator is then turned on and a stabilisation
time is provided before releasing CPU operation.
The stabilisation time is 4096 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Note
The Halt mode cannot be used when the
watchdog or the Safeguard are enabled, if the
HALT instruction is executed while the watchdog
or safeguard system are enabled, a reset is auto-
matically generated thus resetting the entire MCU.
Note
Halt Mode affects only the digital section of
the device. All the analog circuit remain in their
status, including ADC, voltage regulators, bus
transceivers and power bridge.
Figure 13. Halt Mode Flow Chart
N
N
EXTERNAL
INTERRUPT
RESET
HALT INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
ON
SET
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
OFF
OFF
OFF
CLEARED
Y
Y
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