參數(shù)資料
型號: L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
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文件大?。?/td> 853K
代理商: L9805
54/103
L9805
5.4 PWM I/O
5.4.1 Introduction
The PWM I/O interface is a circuit able to connect
internal logic circuits with external high voltage
lines.
The two interfaces represent respectively the re-
ceiver and the transmitter section of a standard
IS0 9141 transceiver.
Connecting PWMO and PWMI together a stand-
ard K bus (ISO 9141) can be realized.
Voltage thresholds are referred to the battery volt-
age connected to VBR pin. This pin must be used
as reference for the K bus. Voltage drops between
this pin and the battery line can cause thresholds
mismatch between the L9805 ISO trasceiver and
the counterpart trasceiver(s) connected to the
same bus line.
See
Figure 29
for a block diagram description of
the two interfaces.
Figure 29. PWM I/O Block Diagram
5.4.2 PWMO
PWMO is an output line, directly driven by the
PWM2 output signal. The circuit translates the log-
ic levels of PWM2 output to voltage levels referred
to the VB supply (see
Figure 29
). When PWM2=0
the open drain is switched off, in the other case the
PWMO line is pulled down by the open drain driv-
er.
PWMO is protected against short circuit to battery
by a dedicated circuit that limits the current sunk
by the output transistor. When the limiter is activat-
ed the voltage on PWMO pin rises up. If the limiter
remains active for more than 25
μ
s the driver is
switched off.
If the battery or ground connection are lost, the
PWMO line shows a controlled impedance charac-
teristic (see
Figure 30
).
PWM0 is high at NRESET is asserted.
Figure 30. Impedance at PWMO/I pin
5.4.3 PWMI
PWMI is an input line, directly connected to PB2
bit. The circuit translates the voltage levels re-
ferred to VB voltage supply to the internal logic lev-
els (see
Figure 29
). When the voltage on PWMI
VDD
PWMO
VDD
TIMER CAPTURE INPUT
PWM2 OUTPUT
PB2 REGISTER BIT
-
+
PWMI
VBR
Battery
K bus
50K
50K
5
μ
A
V
K
I
K
14V
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