參數(shù)資料
型號: L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動馬達(dá)驅(qū)動器,帶有8位微控制器,CAN接口,16K的存儲器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時器,2個PWM模塊,涪陵
文件頁數(shù): 62/103頁
文件大?。?/td> 853K
代理商: L9805
62/103
L9805
CONTROLLER AREA NETWORK
(Cont’d)
5.6.3.3 Modes of Operation
The CAN Core unit assumes one of the seven
states described below:
STANDBY
. Stand-by mode is entered either on
a chip reset or on resetting the RUN bit in the
Control/Status Register (CSR). Any on-going
transmission or reception operation is not inter-
rupted and completes normally before the Bit
Time Logic and the clock prescaler are turned off
for minimum power consumption. This state is
signalled by the RUN bit being read-back as 0.
Once in stand-by, the only event monitored is the
reception of a dominant bit which causes a wake-
up interrupt if the SCIE bit of the Interrupt Control
Register (ICR) is set.
The STANDBY mode is left by setting the RUN
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
nism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
WAKE-UP
. The CAN bus line is forced to domi-
nant for one bit time signalling the wake-up con-
dition to all other bus members.
Figure 36. CAN Controller State Diagram
n
n
n
n
n
n
n
STANDBY
RESYNC
WAKE-UP
RECEPTION
TRANSMISSION
ERROR
IDLE
ARESET
RUN
RUN & WKPS
RUN & WKPS
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RUN
Write to DATA7 |
TX Error & NRTX
Start Of Frame
Arbitration lost
TX Error
RX Error
TX OK
RX OK
BOFF
BOFF
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