參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計(jì)
文件頁數(shù)： 97/135頁
文件大小： 585K
代理商： DS3112RD
DS3112
97 of 135
TFL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TFL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TFL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TFL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TRANSMIT FIFO LEVEL
empty to 15 bytes
16 to 31 bytes
32 to 47 bytes
48 to 63 bytes
64 to 79 bytes
80 to 95 bytes
96 to 111 bytes
112 to 127 bytes
128 to 143 bytes
144 to 159 bytes
160 to 175 bytes
176 to 191 bytes
192 to 207 bytes
208 to 223 bytes
224 to 239 bytes
240 to 256 bytes
Bit 12/Transmit FIFO Empty (TEMPTY).
This read-only real-time status bit will be set to a one when
the transmit FIFO is empty. It will be cleared when the transmit FIFO contains one or more bytes. This
status bit cannot cause a hardware interrupt.
Bit 13/Receive FIFO Overrun (ROVR).
This latched read-only event-status bit will be set to a one each
time the receive FIFO overruns. This bit will be cleared when read and will not be set again until another
overrun occurs (i.e., the FIFO has been read from and then allowed to fill up again). The setting of this bit
can cause a hardware interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR) register is
set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bit 14/Receive FIFO Empty (REMPTY).
This real-time bit will be set to a one when the Receive FIFO
is empty and will be set to a zero when the Receive FIFO is not empty.
Bit 15/Receive Abort Sequence Detected (RABT).
This latched read-only event-status bit will be set to
a one each time the receive HDLC controller detects seven or more ones in a row during packet reception.
If the receive HDLC is not currently receiving a packet, then seven or more ones in a row will not trigger
this status bit. This bit will be cleared when read and will not be set again until another abort is detected
(at least one valid flag must be detected before another abort can be detected). The setting of this bit can
cause a hardware interrupt to occur if the RABT bit in the Interrupt Mask for HSR (IHSR) register is set
to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt
will be allowed to clear when this bit is read.
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