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參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計 |
| 文件頁數(shù)： | 4/135頁 |
| 文件大小： | 585K |
| 代理商： | DS3112RD |
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DS3112
4 of 135
1. INTRODUCTION
The DS3112 TEMPE (
T
3
E
3
M
ulti
P
lex
E
When the device is used as a multiplexer, it can be operated in one of three modes:
M13 – multiplex 28 T1 lines into a T3 data stream
E13 – multiplex 16 E1 lines into a E3 data stream
G.747 – multiplex 21 E1 lines into a T3 data stream
See Figures 1A, 1B, and 1C for block diagrams of these three modes. In each of the block diagrams, the
receive section is at the bottom and the transmit section is at the top. The receive path is defined as
incoming T3/E3 data and the transmit path is defined as outgoing T3/E3 data. When the device is
operated solely as a T3 or E3 framer, the multiplexer portion of the device is disabled and the raw T3/E3
payload will be output at the FRD output and input at the FTD input. See Figures 1A and 1B for details.
In the receive path, raw T3/E3 data is clocked into the device (either in a bipolar or unipolar fashion) with
the HRCLK at the HRPOS and HRNEG inputs. The data is then framed by the T3/E3 framer and passed
through the two-step demultiplexing process to yield the resultant T1 and E1 data streams, which are
output at the LRCLK and LRDAT outputs. In the transmit path, the reverse occurs. The T1 and E1 data
streams are input to the device at the LTCLK and LTDAT inputs. The device will sample these inputs
and then multiplex the T1 and E1 data streams through a two-step multiplexing process to yield the
resultant T3 or E3 data stream. Then this data stream is passed through the T3/E3 formatter to have the
framing overhead added, and the final data stream to be transmitted is output at the HTPOS and HTNEG
outputs using the HTCLK output.
The DS3112 has been designed to meet all of the latest telecommunications standards. Table 1A lists all
of the applicable standards for the device.
The TEMPE device has a number of advanced features such as:
§
the ability to drop and insert up to two T1 or E1 ports
§
an onboard HDLC controller with 256-byte buffers
§
an onboard Bit Error Rate Tester (BERT)
§
advanced diagnostics to create and detect many different types of errors
See Table 1B for a complete list of main features within the device.
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