參數資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復用器參考設計
文件頁數： 54/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
54 of 135
Bit 3/Remote Alarm Indication Detected (RAI).
This latched read-only alarm status bit will be set to a
one when the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will
be cleared when read unless an RAI signal is still present. A change in state of the RAI detection can
cause a hardware interrupt to occur if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is
set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read. The RAI alarm detection criteria is described in
Tables 5.3A and 5.3B. RAI can also be indicated via the FEAC codes when the device is operated in the
C-Bit Parity Mode.
Bit 4/T3 Idle Signal Detected (T3IDLE).
This latched read-only alarm status bit will be set to a one
when the T3 framer detects an incoming idle signal. This bit will be cleared when read unless the idle
signal is still present. A change in state of idle detection can cause a hardware interrupt to occur if the
IDLE bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The IDLE detection criteria is described in Table
5.3A. The interrupt will be allowed to clear when this bit is read. When the DS3112 is operated in the E3
mode, this status bit should be ignored.
Bit 5/Transmit T3/E3 Start Of Frame (TSOF).
This latched read-only event-status bit will be set to a
one on each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal
and it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the
TSOF bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 6/Receive T3/E3 Start Of Frame (RSOF).
This latched read-only event status bit will be set to a one
on each T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and
it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the RSOF
bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one.
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