- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376976 > DS3112RD (Maxim Integrated Products, Inc.) RECT BRIDGE GPP 15A 800V GBJ PDF資料下載
參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復用器參考設計 |
| 文件頁數(shù)： | 19/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁
DS3112
19 of 135
2.3 T3/E3 Receive Framer Signal Description
Signal Name:
FRSOF
Signal Description:
T3/E3 Receive Framer Start Of Frame Sync Signal
Signal Type:
Output
This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary (Figure 2.3A). This
signal can be configured via the FRSOFI control bit in Master Control Register 3 (Section 4.2) to be
either active high (normal mode) or active low (inverted mode).
Signal Name:
FRCLK
Signal Description:
T3/E3 Receive Framer Clock
Signal Type:
Output
This signal outputs the clock that is used to pass data through the receive T3/E3 framer. It can be sourced
from either the HRCLK or FTCLK inputs (Figures 1A and 1B). This signal is used to clock the receive
data out of the device at the FRD output. Data can be either updated on a rising edge (normal mode) or a
falling edge (inverted mode). This option is controlled via the FRCLKI control bit in Master Control
Register 3 (Section 4.2).
Signal Name:
FRD
Signal Description:
T3/E3 Receive Framer Serial Data
Signal Type:
Output
This signal outputs data from the receive T3/E3 framer. This signal is updated either on the rising edge of
FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). This option is controlled via the
FRCLKI control bit in Master Control Register 3 (Section 4.2). Also, this signal can be internally inverted
if enabled via the FRDI control bit in Master Control Register 3 (Section 4.2).
Signal Name:
FRDEN
Signal Description:
T3/E3 Receive Framer Serial Data Enable or Gapped Clock Output
Signal Type:
Output
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a
data enable or a gapped clock. In the data enable mode, this signal will go active when payload data is
available at the FRD output and it will go inactive when overhead data is being output at the FRD output.
In the gapped clock mode, this signal will transition for each bit of payload data and will be suppressed
for each bit of overhead data. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X
Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits
1 to 12). See Figure 2.3A for an example. This signal can be internally inverted if enabled via the
FRDENI control bit in Master Control Register 3 (Section 4.2).
Signal Name:
FRMECU
Signal Description:
T3/E3 Receive Framer Manual Error Counter Update Strobe
Signal Type:
Input
Via the AECU control bit in Master Control Register 1 (Section 4.2), the DS3112 can be configured to
use this asynchronous input to initiate an updating of the internal error counters. A zero to one transition
on this input causes the device to begin loading the internal error counters with the latest error counts.
This signal must be returned low before a subsequent updating of the error counters can occur. The host
must wait at least 100ns before reading the error counters to allow the device time to update the error
counters. This signal is logically OR’ed with the MECU control bit in Master Control Register 1. If this
signal is not used, then it should be tied low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3116MP000 | 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F |
| DS311X | 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 類別:盒，外殼，支架 >> 插線臺，插座面板 - 配件 系列:Kwik-Change® 標準包裝:50 系列:- 附件類型:模擬插頭，雙 樣式:耳機，0.173" 直徑 包括:- |
| DS312 | 功能描述:插線板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| DS-312 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz |
| DS312_09 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information |
發(fā)布緊急采購，3分鐘左右您將得到回復。