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參數(shù)資料
| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁數(shù)： | 91/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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Transmit Operation
On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by
either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then
waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero
stuff the outgoing data stream. When the transmit HDLC controller detects that the TMEND bit in the
transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a
closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If
there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag
and begin sending the next packet. Between consecutive packets, there are always at least two flags of
7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e., before the TMEND bit is set),
then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a
continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)
status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the host.
The transmit HDLC has been designed to minimize its real-time host support requirements. The transmit
FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that need to be sent once a second. Hence in T3 applications, the host only needs to access the
transmit HDLC once a second to load up the three messages. Once the host has loaded an outgoing
packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has finished
being transmitted. Also, the host can be notified when the FIFO has emptied below a programmable level
called the low watermark. The host must never overfill the FIFO. To keep this from occurring, the host
can obtain the real-time depth of the transmit FIFO via the Transmit FIFO Level bits in the HDLC Status
Register (HSR).
9.2 HDLC Control and FIFO Register Description
Register Name:
HCR
Register Description:
HDLC Control Register
Register Address:
80h
Bit #
7
6
5
4
Name
n/a
RHR
THR
TFS
Default
-
0
0
0
Bit #
15
14
13
Name
RHWMS2
RHWMS1
RHWMS0
TLWMS2
Default
0
0
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit CRC Defeat (TCRCD).
When this bit is set low, the HDLC will automatically calculate
and append the 16-bit CRC to the outgoing HDLC message. When this bit is set high, the device will not
append the CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
3
n/a
-
2
1
0
TCRCI
-
TZSD
0
TCRCD
0
12
11
10
9
8
TLWMS1
0
TLWMS0 RID
0
TID
0
0
0
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