參數(shù)資料
型號: DS3112RD
廠商: Maxim Integrated Products, Inc.
英文描述: RECT BRIDGE GPP 15A 800V GBJ
中文描述: DS3/E3多路復(fù)用器參考設(shè)計
文件頁數(shù): 75/135頁
文件大小: 585K
代理商: DS3112RD
DS3112
75 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15 / T1/E1 Diagnostic Loopback Enable for Ports 1 to 16 (DLB1 to DLB16).
These bits
enable or disable the T1/E1 Diagnostic LoopBack (DLB). See the block diagrams in Section 1 for a
visual description of this loopback. DLB1 corresponds to T1/E1 Port 1, DLB2 corresponds to T1/E1 Port
2, and so on. If the device is configured in Low Speed T1/E1 Port Loop Timed mode (if LLTM bit in the
MC1 register is set to a one) then only data will be looped back—the clock will not be looped back. Since
ports 4, 8, 12, 16, 20, 24, and 28 are not active in the G.747 mode, the DLB4, DLB8, DLB12, and DLB16
bits have no effect in the G.747 mode.
0 = disable loopback
1 = enable loopback
Register Name:
T1E1DLB2
Register Description:
T1/E1 Diagnostic Loopback Control Register 2
Register Address:
56h
Bit #
7
6
5
4
Name
DLB24
DLB23
DLB22
DLB21
Default
0
0
0
0
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
T1E1DLB1
T1/E1 Diagnostic Loopback Control Register 1
54h
7
6
5
4
3
2
1
0
DLB8
0
DLB7
0
DLB6
0
DLB5
0
DLB4
0
DLB3
0
DLB2
0
DLB1
0
15
14
13
12
11
10
9
8
DLB16
0
DLB15
0
DLB14
0
DLB13
0
DLB12
0
DLB11
0
DLB10
0
DLB9
0
3
2
1
0
DLB20
0
DLB19
0
DLB18
0
DLB17
0
11
10
9
8
DLB28
0
DLB27
0
DLB26
0
DLB25
0
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