參數(shù)資料
型號(hào)： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計(jì)
文件頁數(shù)： 83/135頁
文件大小： 585K
代理商： DS3112RD
DS3112
83 of 135
TBPS4:0
10100 Port 20
10101 Port 21
10110 Port 22
10111 Port 23
11100 Port 28
11101 T3/E3 Framer (payload bits only)
11110 T3/E3 Framer (payload + overhead bits)
11111 Illegal State
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Force Resynchronization (RESYNC).
A low to high transition will force the receive BERT
synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high
whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a
subsequent resynchronization.
Bit 1/Load Bit and Error Counters (LC).
A low to high transition latches the current bit and error
counts into the host accessible registers BERTBC and BERTEC and clears the internal count. This bit
should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be
cleared and set again for a subsequent loads.
Bits 2 to 4/Pattern Select Bits 0 (PS0 to PS2).
If PBS = 0:
000 = Pseudorandom Pattern 2
7
- 1 (ANSI T1.403-1999 Annex B)
001 = Pseudorandom Pattern 2
11
- 1 (ITU O.153)
010 = Pseudorandom Pattern 2
15
- 1 (ITU O.151)
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
If PBS = 1:
000 = Psuedorandom Pattern 2
9
- 1
001 = Pseudorandom Pattern 2
20
- 1 (non-QRSS)
010 = Pseudorandom Pattern 2
23
- 1 (ITU O.151)
011 = Illegal State
10X = Illegal State (X = 0 or 1)
11X = lllegal State (X = 0 or 1)
BERTC0
BERT Control Register 0
70h
7
6
5
4
3
2
1
0
PBS
0
TINV
0
RINV
0
PS2
0
PS1
0
PS0
0
LC
0
RESYNC
0
15
14
13
12
n/a
-
11
10
9
8
IESYNC
0
IEBED
0
IEOF
0
RPL3
0
RPL2
0
RPL1
0
RPL0
0
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