參數(shù)資料
型號(hào)： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計(jì)
文件頁數(shù)： 20/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
20 of 135
Signal Name:
Signal Description:
Signal Type:
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Signal (LOS) state. It will
remain high as long as the LOS state persists and will return low when the framer exits the LOS state. See
Section 5.3 for details on the set and clear criteria for this signal. LOS status is also available via a
software bit in the T3/E3 Status Register (Section 5.3).
Signal Name:
FRLOF
Signal Description:
T3/E3 Receive Framer Loss Of Frame
Signal Type:
Output
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Frame (LOF) state. It will
remain high as long as the LOF state persists and will return low when the framer synchronizes. See
Section 5.3 for details on the set and clear criteria for this signal. LOF status is also available via a
software bit in the T3/E3 Status Register (Section 5.3).
T3/E3 RECEIVE FRAMER TIMING
Figure 2.3A
FRLOS
T3/E3 Receive Framer Loss Of Signal
Output
FRCLK
Normal Mode
FRD
(see note)
T3: X1
E3: Bit 1 of FAS
Last Bit of
the Frame
FRCLK
Inverted Mode
FRDEN
Data Enable Mode for T3
(see note)
FRDEN
Data Enable Mode for
E3
FRDEN
Gapped Clock Mode for T3
(see note)
FRDEN
Gapped Clock Mode for E3
(see note)
FRSOF
(see note)
Note: FRD, FRDEN, and FRSOF can be inverted via Master Control Register
3.
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