- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376976 > DS3112RD (Maxim Integrated Products, Inc.) RECT BRIDGE GPP 15A 800V GBJ PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 6/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)
DS3112
6 of 135
MAIN DS3112 TEMPE FEATURES
Table 1B
General Features
§
Can be operated as a standalone T3 or E3 framer without any M13 or E13 multiplexing
§
T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter
§
Two T1/E1 drop and insert ports
§
B3ZS/HDB3 encoder and decoder
§
T3 C-Bit Parity mode
§
All the receive T1/E1 ports can be clocked out on a common clock
§
All the transmit T1/E1 ports can be clocked in on a common clock
§
Generates gapped clocks that can be used as demand clocks in unchannelized T3/E3 applications
§
T1/E1 ports can be configured into a “l(fā)oop-timed” mode
§
T3/E3 port interfaces can be either bipolar or unipolar
§
The clock, data, and control signals can be inverted to allow a glueless interface to other device
§
Loss of transmit and receive clock detect
T3/E3 Framer
§
Generates T3/E3 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms
§
Transmit framer pass through mode
§
Generates T3 idle signal
§
Detects the following T3/E3 alarms and events: Loss Of Signal (LOS), Loss Of Frame (LOF), Alarm
Indication Signal (AIS), Remote Alarm Indication (RAI), T3 idle signal, Change Of Frame Alignment
(COFA), B3ZS and HDB3 code words being received, Severely Errored Framing Event (SEFE), and
T3 Application ID status indication
T2/E2 Framer
§
Generates T2/E2 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms
§
Generates Alarm Indication Signal (AIS) for T1/E1 data streams in both the transmit and receive
directions
§
Detects the following T2/E2 alarms and events: Loss Of Frame (LOF), Alarm Indication Signal
(AIS), and Remote Alarm Indication (RAI)
§
Detects T1 line loopback commands (C3 bit is the inverse of C1 and C2)
§
Generates T1 line loopback commands
HDLC Controller
§
Designed to handle multiple LAPD messages without Host intervention
§
256 byte receive and transmit buffers are large enough to handle the three T3 messages (Path ID, Idle
Signal ID, and Test Signal ID) that are sent and received once a second which means the Host only
needs to access the HDLC Controller once a second
§
Handles all of the normal Layer 2 tasks such as zero stuffing/destuffing, CRC generation/checking,
abort generation/checking, flag generation/detection, and byte alignment
§
Programmable high and low watermarks for the FIFO
§
HDLC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3116MP000 | 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F |
| DS311X | 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 類(lèi)別:盒，外殼，支架 >> 插線臺(tái)，插座面板 - 配件 系列:Kwik-Change® 標(biāo)準(zhǔn)包裝:50 系列:- 附件類(lèi)型:模擬插頭，雙 樣式:耳機(jī)，0.173" 直徑 包括:- |
| DS312 | 功能描述:插線板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 產(chǎn)品類(lèi)型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類(lèi)型: 位置/觸點(diǎn)數(shù)量:48 |
| DS-312 | 制造商:MA-COM 制造商全稱(chēng):M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz |
| DS312_09 | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。