參數資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復用器參考設計
文件頁數： 53/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
53 of 135
5.3 T3/E3 Framer Status and Interrupt Register Description
Register Name:
T3E3SR
Register Description:
T3/E3 Status Register
Register Address:
12h
Bit #
7
6
5
Name
n/a
RSOF
TSOF
Default
-
-
-
Bit #
15
14
13
Name
n/a
n/a
n/a
Default
-
-
-
Note:
See Figure 5.3A for details on the signal flow for the status bits in the T3E3SR register.
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Loss Of Signal Occurrence (LOS).
This latched read-only alarm-status bit will be set to a one
when the T3 or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS
condition still exists. A change in state of the LOS can cause a hardware interrupt to occur if the LOS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The LOS alarm criteria is described in Tables 5.3A and 5.3B.
Bit 1/Loss Of Frame Occurrence (LOF).
This latched read-only alarm status bit will be set to a one
when the T3 or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF
condition still exists. A change in state of the LOF can cause a hardware interrupt to occur if the LOF bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The LOF alarm criteria is described in Tables 5.3A and 5.3B.
Bit 2/Alarm Indication Signal Detected (AIS).
This latched read-only alarm-status bit will be set to a
one when the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared when
read unless an AIS signal is still present. A change in state of the AIS detection can cause a hardware
interrupt to occur if the AIS bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and
the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when this bit is read. The AIS alarm detection criteria is described in Tables 5.3A and
5.3B.
4
3
2
1
0
T3IDLE
-
RAI
-
AIS
-
LOF
-
LOS
-
12
n/a
-
11
n/a
-
10
n/a
-
9
8
n/a
-
n/a
-
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