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| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 65/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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Bits 0 to 6/T2/E2/G.747 Transmit Remote Alarm Indication (TRAIn where n = 1 to 7).
When this
bit is set high in the T3 mode, the X bit will be set to zero. When this bit is set high in the E3 mode, the
RAI bit (bit number 11 of each E2 frame) will be set to a one. In the E3 mode, TRAI5 to TRAI7 (bits 4 to
6) are disabled and should be set low by the host. When this bit is set high in the G.747 mode, the RAI bit
(bit number 1 of Set 2 in each G.747 frame) will be set to a one. When this bit it set low in the T3 mode,
the X bit will be set to a one. When this bit is set low in the E3 and G.747 modes, the RAI bit will be set
to zero.
0 = do not transmit RAI
1 = transmit RAI
Bits 8 to 14/T2/E2/G.747 Transmit Alarm Indication Signal (TAISn where n = 1 to 7).
When this bit
is set high, the transmit formatter will generate an unframed all ones pattern. When this bit it set low,
normal data is transmitted. In the E3 mode, TAIS5 to TAIS7 (bits 4 to 6) are disabled and should be set
low by the host.
0 = do not transmit AIS
1 = transmit AIS
Register Name:
T2E2CR2
Register Description:
T2/E2 Control Register 2
Register Address:
32h
Bit #
7
6
5
4
Name
n/a
LOFG7
LOFG6
LOFG5
Default
-
0
0
0
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 6/T2/E2/G.747 Transmit Loss Of Frame Generation (LOFGn where n = 1 to 7).
A zero to
one transition on this bit will cause the T2/E2/G.747 transmit formatter to generate enough framing bit
errors to cause the far end to lose frame synchronization. This bit must be cleared and set again for a
subsequent set of errors to be generated.
FRAMING ERRORS GENERATED
T3 Mode
Four consecutive F bit errors
Four consecutive FAS words of 0000101111 generated instead of the normal
FAS word, which is 1111010000 (i.e., all FAS bits are inverted)
Four consecutive FAS words of 000101111 generated instead of the normal
FAS word, which is 111010000 (i.e., all FAS bits are inverted)
Bits 8 to 11 / E2 Transmit National Bit Setting (E2Snn where n = 1 to 4).
These bits are ignored in
the T3 and G.747 modes. The received Sn can be read from the T2E2 Status Register 2.
0 = force the Sn bit to zero
1 = force the Sn bit to one
3
2
1
0
LOFG4
0
LOFG3
0
LOFG2
0
LOFG1
0
11
10
9
8
E2Sn4
-
E2Sn3
-
E2Sn2
-
E2Sn1
-
E3 Mode
G.747 Mode
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