參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計
文件頁數(shù)： 18/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
18 of 135
Signal Name:
Signal Description:
Signal Type:
The external host will configure the device and obtain real time status information about the device via
these signals. When reading data from the CPU Bus, these signals will be outputs. When writing data to
the CPU Bus, these signals will become inputs. When the CPU bus is operated in the 8-bit mode
(CMS = 1), CD8 to CD15 are inactive and should be tied low.
Signal Name:
CA0 to CA7
Signal Description:
CPU Bus Address Bus
Signal Type:
Input
These input signals determine which internal device configuration register that the external host wishes to
access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be tied
low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant address bit.
Signal Name:
CWR* (CR/W*)
Signal Description:
CPU Bus Write Enable (CPU Bus Read/Write Select)
Signal Type:
Input
In Intel Mode (CIM = 0), this signal will determine when data is to be written to the device. In Motorola
Mode (CIM = 1), this signal will be used to determine whether a read or write is to occur.
Signal Name:
CRD* (CDS*)
Signal Description:
CPU Bus Read Enable (CPU Bus Data Strobe)
Signal Type:
Input
In Intel Mode (CIM = 0) this signal will determine when data is to be read from the device. In Motorola
Mode (CIM = 1), a rising edge will be used to write data into the device.
Signal Name:
CINT*
Signal Description:
CPU Bus Interrupt
Signal Type:
Output (Open Drain)
This signal is an open-drain output which will be forced low if one or more unmasked interrupt sources
within the device is active. The signal will remain low until either the interrupt is serviced or masked.
Signal Name:
CCS*
Signal Description:
CPU Bus Chip Select
Signal Type:
Input
This active low signal must be asserted for the device to accept a read or write command from an external
host.
Signal Name:
CALE
Signal Description:
CPU Bus Address Latch Enable
Signal Type:
Input
This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
non-multiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0]
should be tied to CD[7:0] and the falling edge of CALE will latch the address.
CD0 to CD15
CPU Bus Data Bus
Input/Output (3-State Capable)
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