參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復用器參考設計
文件頁數(shù)： 78/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
78 of 135
7.3 T1 Line Loopback Command Status Register Description
Register Name:
T1LBSR1
Register Description:
T1 Line Loopback Command Status Register 1
Register Address:
5Ch
Bit #
7
6
5
Name
LLB8
LLB7
LLB6
Default
-
-
-
Bit #
15
14
13
Name
LLB16
LLB15
LLB14
Default
-
-
-
Note:
See Figure 7.3A for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2
registers.
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/T1 Line Loopback Command Status for Ports 1 to 16 (LLB1 to LLB16).
These read-only
real-time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the
inverse of the C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3
bit is not the inverse of the C1 and C2 bits for five consecutive frames. LLB1 corresponds to T1/E1 Port
1, LLB2 corresponds to T1/E1 Port 2, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2
can cause a hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a
one. In the E3 and G.747 modes, these bits are meaningless and should be ignored.
Register Name:
T1LBSR2
Register Description:
T1 Line Loopback Command Status Register 2
Register Address:
5Eh
Bit #
7
6
5
4
Name
LLB24
LLB23
LLB22
LLB21
Default
-
-
-
-
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
4
3
2
1
0
LLB5
-
LLB4
-
LLB3
-
LLB2
-
LLB1
-
12
11
10
9
8
LLB13
-
LLB12
-
LLB11
-
LLB10
-
LLB9
-
3
2
1
0
LLB20
-
LLB19
-
LLB18
-
LLB17
-
11
10
9
8
LLB28
-
LLB27
-
LLB26
-
LLB25
-
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