參數(shù)資料
型號(hào)： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計(jì)
文件頁(yè)數(shù)： 38/135頁(yè)
文件大小： 585K
代理商： DS3112RD
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DS3112
38 of 135
REAL-TIME STATUS BIT
Figure 4.3C
A Note about the MSR
The Master Status Register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:
MSR
Register Description:
Master Status Register
Register Address:
08h
Bit #
7
6
5
4
Name
n/a
T2E2SR2
T2E2SR1
FEAC
Default
-
-
-
-
Bit #
15
14
13
12
Name
n/a
n/a
G.747
T3E3MS
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/One-Second Timer Boundary Occurrence (OST).
This latched read-only event-status bit will be
set to a one on each one-second boundary as timed by the DS3112. The device chooses an arbitrary one
second boundary that is timed from the HRCLK signal. This bit will be cleared when read and will not be
set again until another one-second boundary has occurred. The setting of this status bit can cause a
hardware interrupt to occur if the OST bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
The interrupt will be allowed to clear when this bit is read.
Bit 1/Counter Overflow Event (COVF).
This latched read-only event-status bit will be set to a one if
any of the error counters saturates (the error counters saturate when full). This bit will be cleared when
read even if one or more of the error counters is still saturated. The setting of this status bit can cause a
hardware interrupt to occur if the COVF bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read.
3
2
1
0
HDLC
-
BERT
-
COVF
-
OST
-
11
10
9
8
LORC
-
LOTC
-
T3E3SR
-
T1LB
-
Internal Signal
Status Bit
Interrupt
Read
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