參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復用器參考設計
文件頁數(shù)： 25/135頁
文件大小： 585K
代理商： DS3112RD
DS3112
25 of 135
Signal Name:
Signal Description:
Signal Type:
These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any of
the 16/21 E1 data streams (Section 7.4). Data can be clocked into the device either on falling edges
(normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This option is
controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be
internally inverted before being multiplexed if enabled via the LTDATI control bit in Master Control
Register 2 (Section 4.2). When the M13 / E13 multiplexer is disabled, then these inputs are ignored and
should be tied low.
Signal Name:
LTCLKA/LTCLKB
Signal Description:
Low Speed (T1 or E1) Transmit Insert Port Serial Clock Inputs
Signal Type:
Input
These two input signals are used to clock data into the device that will be inserted into one of the 28 T1
data streams or into one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at
the associated LTDAT signals can be clocked into the device either on falling edges (normal clock mode)
or rising edges (inverted clock mode) of LTCLKA/LTCLKB. This option is controlled via the LTCLKI
control bit in Master Control Register 2 (Section 4.2). When the M13 / E13 multiplexer is disabled, then
these inputs are ignored and should be tied low.
Signal Name:
LTCCLK
Signal Description:
Low Speed (T1 or E1) Transmit Common Clock Input
Signal Type:
Input
If enabled via the LTCCEN in Master Control Register 1 (Section 4.2), all 28 LTCLK or 16 LTCLK
signals are disabled and all the data at the 28 LTDAT or 16 LTDAT inputs (as well as the LTDATA and
LTDATB inputs) will be clocked into the device using the LTCCLK signal. In T3 mode, LTCCLK would
be a 1.544MHz clock and in E3 mode, LTCCLK would be 2.048MHz. If not used, this signal should be
tied low. If this signal is used, then all of the LTCLK signals should be tied low. This signal can be
internally inverted. This option is controlled via the LTCLKI control bit in Master Control Register 2
(Section 4.2).
LTDATA/LTDATB
Low Speed (T1 or E1) Transmit Insert Port Serial Data Inputs
Input
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