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| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 88/135頁(yè) |
| 文件大小： | 585K |
| 代理商： | DS3112RD |
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DS3112
88 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Real-Time Synchronization Status (SYNC).
Read-only real-time status of the synchronizer (this
bit is not latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will
be cleared when six or more bits out of 64 are received in error.
Bit 1/BERT Error Counter Overflow (BECO).
A latched read-only event-status bit that is set when the
24-bit BERT Error Counter (BEC) saturates. Cleared when read and will not be set again until another
overflow occurs (i.e., the BEC counter must be cleared and allowed to overflow again). The setting of this
status bit can cause a hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a
one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when this bit is read (Figure 8.2A).
Bit 2/BERT Bit Counter Overflow (BBCO).
A latched read-only event-status bit that is set when the
32-bit BERT Bit Counter (BBC) saturates. Cleared when read and will not be set again until another
overflow occurs (i.e., the BBC counter must be cleared and allowed to overflow again). The setting of
this status bit can cause a hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to
a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read (Figure 8.2A).
Bit 3/Bit Error Detected (BED).
A latched read-only event status bit that is set when a bit error is
detected. The receive BERT must be in synchronization for it to detect bit errors. This bit will be cleared
when read. The setting of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT
Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set
to a one. The interrupt will be allowed to clear when this bit is read (Figure 8.2A).
Bit 4/Receive Loss Of Synchronization (RLOS).
A latched read-only alarm-status bit that is set
whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit will
remain set until read. A change in this status bit (i.e., the synchronizer goes into or out of
synchronization) can cause a hardware interrupt to occur if the IESYNC bit in BERT Control Register 0
is set to a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read (Figure 8.2A).
Bit 5/Receive All Zeros (RA0).
A latched read-only alarm-status bit that is set when 31 consecutive
zeros are received. Allowed to be cleared once a one is received.
BERTEC0
BERT 24-Bit Error Counter (lower) and Status Information
7Ch
7
6
5
4
3
2
1
0
n/a
-
RA1
-
RA0
-
RLOS
-
BED
-
BBCO
-
BECO
-
SYNC
-
15
14
13
12
11
10
9
8
BEC7
0
BEC6
0
BEC5
0
BEC4
0
BEC3
0
BEC2
0
BEC1
0
BEC0
0
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