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參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復用器參考設計 |
| 文件頁數(shù)： | 33/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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Bit 2/T3 C-Bit Parity Mode Enable (CBEN).
This bit is only active when the device is T3 mode. When
this bit is set low, C-Bit Parity is defeated and the C Bits are sourced from the M23 Multiplexer Block
(Figure 1A). This bit should not be set low in the T3 unchannelized mode (UNCHEN = 1). When this bit
is set high, C-Bit Parity mode is enabled and the C bits are sourced from the T3 framer block (Figures 1A
and 1C).
0 = disable C-Bit Parity mode (also known as the M23 Mode)
1 = enable C-Bit Parity mode
Bit 3/Automatic One-Second Error Counters Update Defeat (AECU).
When this bit is set low, the
device will automatically update the T3/E3 performance error counters on an internally created one
second boundary. The host will be notified of the update via the setting of the OST status bit in the
Master Status Register. In this mode, the host has a full one second period to retrieve the error
information before if will be overwritten with the next update. When this bit is set high, the device will
defeat the automatic one second update and enable a manual update mode. In the manual update mode,
the device relies on either the Framer Manual Error Counter Update (FRMECU) hardware input signal or
the MECU control bit to update the error counters. The FRMECU hardware input signal and MECU
control bit are logically OR’ed and hence a zero to one transition on either will initiate an error counter
update to occur. After either the FRMECU signal or MECU bit has toggled, the host must wait at least
100ns before reading the error counters to allow the device time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
Bit 4/Manual Error Counter Update (MECU).
A zero to one transition on this bit will cause the device
to update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit
must be cleared and set again for a subsequent update. This bit is logically OR’ed with the external
FRMECU hardware input signal. After this bit has toggled, the host must wait at least 100ns before
reading the error counters to allow the device time to complete the update.
Bit 5/High-Speed (T3/E3) Port Unipolar Enable (UNI).
When this bit is set low, the device will output
a bipolar coded signal at HTPOS and HTNEG and expect a bipolar coded signal at HRPOS and HRNEG.
When this bit is set high, the device will output a NRZ coded signal at HTPOS and expect a NRZ coded
signal at HRPOS. In the unipolar mode, the device will force the HTNEG output low and the HRNEG
input is ignored and should be tied low. In the unipolar mode, the B3ZS and HDB3 coder/decoders
should be disabled by setting the ZCSD bit to one (ZCSD = 1).
0 = bipolar mode
1 = unipolar mode
Bit 6/Loss Of Transmit Clock Mux Control (LOTCMC).
The DS3112 can detect if the FTCLK fails to
transition. If this bit is set low, the device will take no action (other than setting the LOTC status bit)
when the FTCLK fails to transition. When this bit is set high, the device will automatically switch to the
input receive clock (HRCLK) when the FTCLK fails and transmit AIS.
0 = do not switch to the HRCLK signal if FTCLK fails to transition
1 = automatically switch to the HRCLK signal if the FTCLK fails to transition and send AIS
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