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參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計 |
| 文件頁數(shù)： | 92/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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Bit 1/Transmit Zero Stuffer Defeat (TZSD).
When this bit is set low, the HDLC will automatically
enable the zero stuffer in between the opening and closing flags of the HDLC message. When this bit is
set high, the device will not enable the zero stuffer under any condition.
0 = enable zero stuffer (normal operation)
1 = disable zero stuffer
Bit 2/Transmit CRC Invert (TCRCI).
When this bit is set low, the HDLC will allow the CRC to be
generated normally. When this bit is set high, the device will invert all 16 bits of the generated CRC. This
bit is ignored when the CRC generation is disabled (TCRCD = 1). This bit is useful in testing HDLC
operation.
0 = do not invert the generated CRC (normal operation)
1 = Invert the generated CRC
Bit 4/Transmit Flag/Idle Select (TFS).
This control bit determines whether flags or idle bytes will be
transmitted in between packets.
0 = 7Eh (flags)
1 = FFh (idle)
Bit 5/Transmit HDLC Reset (THR).
A zero to one transition will reset the Transmit HDLC controller.
Must be cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit
FIFO and cause one FEh abort sequence (7 ones is a row) to be sent followed by either 7Eh (flags) or FFh
(idle) until a new packet is initiated by writing new data (at least 2 bytes) into the FIFO.
Bit 6/Receive HDLC Reset (RHR).
A zero to one transition will reset the Receive HDLC controller.
Must be cleared and set again for a subsequent reset. A reset will flush the current contents of the receive
FIFO and cause the receive HDLC controller to begin searching for a new incoming HDLC packet.
Bit 8/Transmit Invert Data (TID).
The control bit determines whether all of the data from the HDLC
controller (including flags and CRC checksum) will be inverted after processing.
0 = do not invert data (normal operation)
1 = invert all data
Bit 9/Receive Invert Data (RID).
The control bit determines whether all of the data into the HDLC
controller (including flags and CRC checksum) will be inverted before processing.
0 = do not invert data (normal operation)
1 = invert all data
Bits 10 to 12/Transmit Low Watermark Select Bits (TLWMS0 to TLWMS2).
These control bits
determine when the HDLC controller should set the TLWM status bit in the HDLC Status Register
(HSR). When the transmit FIFO contains less than the number of bytes configured by these bits, the
TLWM status bit will be set to a one.
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