參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復用器參考設計
文件頁數(shù)： 68/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
68 of 135
Bits 0 to 6/Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7).
This latched read-only
alarm-status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming
RAI alarm. This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747
framer. A change in state of the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2
status bit (in the MSR register) to be set and a hardware interrupt to occur if the IERAI bit is set to a one
and the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set to a one (Figure 6.3B). The
interrupt will be allowed to clear when this bit is read. The RAI alarm criteria is described in Tables 6.3A,
6.3B, and 6.3C. In the E3 mode, RAI5 to RAI7 (bits 4 to 6) are meaningless and should be ignored.
Bit 7/Interrupt Enable for Remote Alarm Indication Signal (IERAI).
This bit should be set to one if
the host wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the
T2E2SR2 status bit in the MSR register (Figure 6.3B). The T2E2SR2 bit in the Interrupt Mask for the
Master Status Register (IMSR) must also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 11/E2 Receive National Bit (E2Snn when n = 1 to 4).
This read-only real-time status bit
reports the incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is
decoded. The host can use the E2SOF status bit to determine when to read this bit. In the T3 and G.747
modes, this bit is meaningless and should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15/E2 Receive Start Of Frame (E2SOFn where n = 1 to 4).
This latched read-only event-
status bit will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The
setting of this status bit cannot cause an interrupt to occur.
T2E2SR2 STATUS BIT FLOW
Figure 6.3B
Note:
All event and alarm latches above are cleared when the T2E2SR2 register is read.
Alarm Latch
Change in State Detect
RAI1
(T2E2SR2
Bit 0)
Internal RAI
Signal from
T2/E2 Framer 1
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2 Framer 7
OR
Mask
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2
Bit 1)
RAI7
(T2E2SR2
Bit 6)
Mask
T2E2SR2
(IMSR Bit 6)
INT*
Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
Event Latch
Event Latch
Event Latch
相關PDF資料
PDF描述
DS3134 Chateau Channelized T1 And E1 And HDLC Controller
DS3160 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS3171 Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS3171N Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS3172 Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
相關代理商/技術參數(shù)
參數(shù)描述
DS3116MP000 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F
DS311X 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 類別:盒，外殼，支架 >> 插線臺，插座面板 - 配件 系列:Kwik-Change® 標準包裝:50 系列:- 附件類型:模擬插頭，雙 樣式:耳機，0.173" 直徑 包括:-
DS312 功能描述:插線板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48
DS-312 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz
DS312_09 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*