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參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計 |
| 文件頁數(shù)： | 57/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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T3 ALARM CRITERIA
Table 5.3A
ALARM/
CONDITION
AIS
Alarm Indication Signal
Properly framed 1010...
pattern, which is aligned
with the 1 just after each
overhead bit and all C bits
are set to zero
DEFINITION
SET CRITERIA
CLEAR CRITERIA
In each 84-bit information
field, the properly aligned
10... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and all C
bits are majority decoded to
be zero during this time
192 consecutive zeros
In each 84 bit information
field, the properly aligned
10... pattern is detected
with 4 or more bit errors
(out of 84 possible) for
1024 consecutive
information bit fields
(1.95ms)
LOS
Loss Of Signal
(Note 2)
No EXZ events over a
192-bit window that starts
with the first one received
Synchronization occurs
LOF
Loss Of Frame
Too many F bits or M bits
in error
Three or more F bits in
error out of 16 consecutive,
or 2 or more M bits in error
out of four consecutive
X1 and X2 = 0 for four
consecutive M frames
(426μs)
RAI
(Note 1)
Remote Alarm
Indication
(This is also referred to as
SEF/AIS in Bellcore GR-
820)
Inactive: X1 = X2 = 1
Active: X1 = X2 = 0
Properly framed 1100...
pattern, which is aligned
with the 11 just after each
overhead bit and the C
bits in Subframe 3 are
zero.
X1 and X2 = 1 for four
consecutive M frames
(426μs)
Idle Signal
In each 84-bit information
field, the properly aligned
1100... pattern is detected
with less than 4-bit errors
(out of 84 possible) for
1024 consecutive
information bit fields
(1.95ms) and the C bits in
Subframe 3 are majority
decoded to be zero during
this time.
In each 84-bit information
field, the properly aligned
1100... pattern is detected
with four or more bit errors
(out of 84 possible) for
1024 consecutive
information bit fields
(1.95ms)
Note 1:
RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2:
LOS is not defined for unipolar (binary) operation.
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